FERROELECTRIC FIELD-EFFECT TRANSISTORS Pooja Chandrashekar Patil Department of Microelectronics Engineering Rochester Institute of Technology 1 Lomb Memorial Drive

FERROELECTRIC FIELD-EFFECT TRANSISTORS
Pooja Chandrashekar Patil
Department of Microelectronics Engineering
Rochester Institute of Technology
1 Lomb Memorial Drive, Rochester, NY, USA 14623

May 5, 2018
ABSTRACT
Ferroelectric materials are known the exhibit instant polarization on applying an electric field. These properties are used in the manufacturing of non-volatile memory devices because of their fast switching speeds and low power consumption. This paper discusses BaTiO3/SrTiO3 structures having a gate length of 15 ?m for FeFETs. The paper then discusses Hafnium-Zirconium-Oxide (Hf0.8Zr0.2O2) device of 5.5 nm thickness and 1 ?m channel length. Further, the effects of thin films on the electrical properties of the device leads to the study of MoS2-PZT devices having 2 ?m and 200 nm channel lengths. The device scaling issues and mismatched lattices are discussed. Later, Pb(Zr,Ti)O3 (PZT) FeFET of 2 ?m channel length is studied and compared with Si:HfO2 devices for their leakage current and self-depolarization issues. The C-V characteristics, ID-VG curves, ID-VD curves, subthreshold swing, ON/OFF ratio, threshold voltage-shifts and retention capabilities are discussed in detail.
INTRODUCTION
Non-volatile memories are preferred for their faster memory access time and data retention capabilities. These devices have high switching speeds and non-destructive read operations while consuming the lowest powers. The device interprets the shift in threshold voltage as a storage value. These values get stored in the memory at high remnant polarization. The simplest device that represents random-access-memory is the 1-transistor, 1-capcitor (1T/1C) memory structure. The data is stored in the ferroelectric capacitor and is accessed by a transmission gate coupled to bit and word lines from the transistor. This device is however large and cannot be scaled. Hence, materials having high dielectric constant, exhibiting ferroelectric property are annealed at the right temperature to induce ferroelectricity. This paper discusses different materials that are used in the industry for fabricating faster working devices having low power consumption and longer retention capabilities. The paper further discusses the processes done at RIT to fabricate silicon doped hafnium oxide FeFET.
theory
A dielectric is an insulating material which when placed in an electric field exhibits electric polarization. The polar molecules present in the dielectric material are randomly oriented without the presence of electric field. Applying an electric field orients these dipoles and polarizes them. Materials that exhibit spontaneous dipole moment and whose direction can be changed on application of an external electric field is known as ferroelectricity. The materials that exhibit ferroelectricity have not center of symmetry which allows the dipoles to orient in any direction. The direction of polarization in a ferroelectric material under electric field is shown in Figure 1.

Figure 1: Polarization direction in ON state and OFF state 5
Ferroelectric materials exhibit hysteresis loops having P-axis that indicates remnant polarization Pr and E-axis that indicates coercive field Ec. A hysteresis loops is shown in Figure 2. The spontaneous polarization Ps is a function of temperature and tends to vanish at the Curie temperature TC which is known as the transition temperature. Hence the device exhibits ferroelectricity when T < TC.

Figure 2: P-E hysteresis loop 1
Ferroelectric Field-Effect-Transistors are devices that have ferroelectric material as the gate oxide. These devices exhibit non-volatile memory and logic functions. The biggest challenge while manufacturing FeFET is the lattice mismatch between the silicon layer and the ferroelectric layer. Certain materials known as perovskite oxides are the only ones suitable to grow on silicon. Alternatively, a gate stack consisting of various buffer layers is required to minimize the effect of lattice mismatch.
Subthreshold swing of a device describes the exponential behavior of current as a function of voltage. It is the inverse of subthreshold slope and is given by
SS=(2.3 kT)/q (1+ C_d/C_ox ) (1)
where k is the Boltzmann constant, T is the temperature, q is the charge of an electron, Cd is the depletion layer capacitance and Cox is the gate oxide capacitance. 3
Memory window is the amount of threshold voltage shift that is possible in a device. Each threshold voltage shift is interpreted as different storage values. It is given by
Memory Window (??V?_T )= V_(T,OFF )-V_(T,ON)5 (2)

experimental results and discussion
Ferroelectric Field-Effect Transistors have been of interest in the semiconductor industry due to their property of exhibiting negative capacitance and high internal voltage gain. Omor F. Shoron et al., from University of California, Santa Barbara grew heterostructures of BaTiO3¬ thin films on doped SrTiO3 by molecular beam epitaxy and studied their abilities to achieve negative capacitance. A BaTiO3 film of 10 nm thickness was directly grown over 120 nm La-doped (001) SrTiO3 channel. The carrier density of BaTiO3 at 0.15 C/cm2 ferroelectric polarization was ~1014 cm-3, which could be matched with SrTiO3 carrier density of ~1019 cm-3. This charge matching ensured that the ferroelectric BaTiO3 layer did not undergo depolarization. The fabricated BaTiO3/SrTiO3 schematic is as shown in Figure 3 below. Another control sample of undoped, non-ferroelectric SrTiO3 of 10 nm thickness over a 60 nm of 1019 cm-3 doped SrTiO3 was also studied for comparison. Schottky contacts of 150-nm-Au/50-nm-Pt layers were deposited by e-beam evaporation and patterned using photolithography to form parallel plate capacitors of 90 × 90 ?m2, 120 × 150 ?m2 and 150 × 300 ?m2 areas. Using a chlorine-based ICP etch, the BaTiO2 layer was etched off and layers of 150-nm-Au/50-nm-Ti were deposited to make Ohmic contacts. The transistor had a gate length of 15 ?m and a source-drain spacing of 55 ?m.

Figure 3: Schematic of fabricated parallel plate capacitor device. Thin arrows represent electric field lines and thick arrow represents direction of built-in polarization in BaTiO3 2
The C-V characteristics of both these devices were measured at 100 kHz and on comparison showed that the control sample exhibited higher capacitance. This was due to the depletion of SrTiO3 channel, which increases the depletion width for higher electric fields applied at negative bias. Also, the horizontal capacitance was observed to decrease for larger capacitors due to series resistance. On comparing the I-V characteristics of both samples, the current in BaTiO2 was observed to be six orders of magnitude lower than SrTiO3 indicating polarization in BaTiO2 sample due to complete depletion of the carriers. The I-V characteristics of BaTiO2/SrTiO3 is as shown in Figure 4 below.

Figure 4: I-V characteristics of both samples 2
Hysteresis measurements were performed on the samples to observe any threshold voltage shifts. The BaTiO2 sample exhibited anticlockwise hysteresis indicating the behavior of ferroelectric switching, and the switchable polarization was measured to be 7×1012 cm-2, whereas, the control sample was seen to exhibit no such behavior. The transistor made from BaTiO2 was then subjected to different frequencies to understand its C-V characteristics. Due to low electron mobility, the capacitance of the device dropped. This is as shown in Figure 5 below.

Figure 5: C-V characteristics of the FET at different frequencies 2
The ID-VD¬ characteristics of the transistor at different gate voltage sweeps is as shown in Figure 6 below. The pinch-off voltage of the transistor was measured to be -1 V. Due to long channel behavior of the device, no output conductance was observed.

Figure 6: ID-VD¬ characteristics of the transistor at different gate voltage 2
The ID-VG characteristics of the FET showed a 0.5 V shift in the threshold voltage of the device. The ON/OFF ratio of the device was measured to be ~104 with a sub-threshold swing of 190 mV/decade. The ID-VG characteristics of the transistor are as shown in Figure 7 below. The anticlockwise hysteresis observed in the graphs is due to carrier densities in the channel at positive and negative gate voltage sweeps.

Figure 7: (a) ID-VG characteristics on logarithmic scale (b) ID-VG characteristics on linear scale 2
Many materials apart from BaTiO2 also possess exhibit ferroelectricity, and this ferroelectric property of the material depends on its annealing conditions. Korok Chatterjee et al., demonstrated the ferroelectric property of Hafnium-Zirconium-Oxide (Hf0.8Zr0.2O2) layer of 5.5 nm thickness. This was a non-volatile memory device of self-aligned type gate last process. The gate late process was performed to reduce the number of annealing steps after deposition of the gate stack. The n-type FET was fabricated on a fully-depleted SOI layer. The gate stack consisted of 0.2 nm thick SiO2 layer. Hf0.8Zr0.2O2 of 5.5 nm thickness was deposited by ALD. TiN is sputtered over this layer and an RTA performed at 500 ?C for 30 seconds in an N2 ambient induces orthorhombicity in the Hf0.8Zr0.2O2, making it ferroelectric in nature. The SiO2 interlayer dielectric is deposited by PECVD technique and contacts hole are patterned and etched to sputter TiN/Ti/Al to form metal contacts. The process flow for the fabrication of this device is as shown in Figure 8 below.

Figure 8: Process flow (a) 12 nm thermal SiO2 and 150 nm a-Si sacrificial gate (b)Active area etched into buried oxide (BOX) layer and dummy gate patterning (c) As ion implantation and CVD oxide deposition (d) Sacrificial gate removed, SiO2 and HZO deposited, TiN sputtered (e) Gate patterned (f) ILD deposited and metallization. 3
The fabricated device had a width of 50 ?m and channel length of 1 ?m. The device was tested for its ON/OFF states as a function of number of read operations and program/erase operations. It was observed that the channel opposed ferroelectric hysteresis due to trapped charges in the channel when the device used DC sweeps instead of pulses. This was interpreted from the reduction in the ON/OFF ratio of the transistor. The cross-section SEM image of the fabricated device is as shown in Figure 9 below.

Figure 9: SEM image of the fabricated FeFET 3
Repeated switching of polarization in the device results in soft breakdown of the device. This was due to large electric fields in the oxide layer which breakdown the SiO2 and the recovery was due to the locally trapped charges in the Hf0.8Zr0.2O2 layer. The device was observed to breakdown past 107 cycles and its recovery time was noted to be approximately 3 hours of not operating the device. The transfer curves are as shown in Figure 10 below.

Figure 10: ID-VG characteristics of before (black) and after (blue, green, red) breakdown recovery 3
The retention capacity of the device was measured to be 105 seconds and the ON/OFF ratio of the device was seen to reduce at higher temperatures. The device can be optimized further by improving its interfacial properties and by reducing the defect states during clock-wise hysteresis.
To obtain devices that exhibit higher stability, Xiao-Wen Zhang et al., studied the n-type semiconductor behavior of molybdenum dichalcogenide (MoS2). Lead-zirconate-titanate (PZT) was used as the ferroelectric gate and MoS2 formed the channel layer. MoS2-PZT FETs were fabricated by exfoliating MoS¬2 nanosheets over PZT/Pt/Ti/SiO2/Si substrate. The fabricated device is as shown in Figure 11 below.

Figure 11: MoS2¬-PZT FET device 4
The channel length of the device was 2 ?m. This device was scaled to 200 nm to observe the hysteresis behavior of the device. The output characteristics of the device show saturation behavior at higher bias conditions which can be observed in Figure 10.

Figure 12: Output characteristics of the MoS2¬-PZT FET device 4
The device exhibited anti-clockwise hysteresis indicating that the fabricated transistor is ferroelectric. The field effect modulation decreases due to interfacial defects or charge trapping. However, the device exhibited ON/OFF states of 105. To observe the effect of scaling, the channel length of the transistor was scaled to 200 nm. The ON/OFF ratio decreases for shorter channel lengths and it was observed to be 104. Thus, scaling the device did not make any highly significant change in the hysteresis behavior of the device. This however does pave way to scaling the device as it does not exhibit any different characteristics. The retention capacity of the transistor was measured to 104 seconds for both the devices. The transfer characteristics of 2 ?m and 200 nm is as shown in Figure 13.

Figure 13: ID-VG characteristics of (a) 2 ?m channel length and (b) 200 nm channel length 4
The electrical properties of the ferroelectric materials that are processed into thin films degrades due to the formation of random grain boundaries. Another issue with depositing ferroelectric material on silicon substrate, was the unwanted reactions between the Si and ferroelectric layer. To obtain FeFETs having long retention capabilities and low gate leakage currents, a good interface becomes necessary. Hence, Jae Hyo Park et al., analyzed Pb(Zr,Ti)O3 (PZT) and suggested a technique of growing uniform rectangular shaped single grains having (111) orientation by seeding method. This technology was named selectively nucleated lateral crystallization (SNLC). Perovskite PZT grains were grown by seeding Pt layer to form traces of TiOx and PbOx which further react to form PbTi3O7 and PbTiO3¬ at 600 ?C. Single grain boundaries of ~50 ?m were formed and a single transistor was fabricated inside one grain. The SNLC-PZT grain growth schematic is shown in Figure 14.

Figure 14: SNLC-PZT grain growth schematic (a) TiOx and PbOx formation (b) reaction to form PbTiO3, PbZrO3 (c) nucleation of PZT (d) PbTiO3 migration and grain growth 4
The device was fabricated on a p-type silicon substrate having 400 nm SiO2 shallow-trench. ZrTiO4 of 2 nm thickness is RF sputtered to form an inter-diffusion barrier. PZT of 200 nm thickness is also RF sputtered. The sample was rapid-thermally-annealed in an air ambient at 700 ?C to form the PZT seed layer. Annealing the sample at 550 ?C promotes grain growth. The gate electrode of 200 nm Pt is deposited and the Pt/PZT/ZrTiO4 layer is etched to implant PH3 ions that form the source and drain regions for the transistor. Passivation layer of 500 nm SiO2 is deposited and Al metal is used for contacts. The fabricated transistor has a dimensions W/L of 3.5/2 ?m. The process flow for the fabrication of the transistor is as shown in Figure 15.

Figure 15: SNLC FeFET fabrication (a) Formation of 400 nm SiO2 shallow-trench (b) Deposition of ZrTiO4 inter-diffusion barrier layer of 2 m, PZT of 200 nm (c) Seed nucleation at 700 ?C by RTA (d) Furnace anneal for grain growth at 550 ?C, depositing Pt gate electrode of 200 nm (e) Etching and patterning gate (f) PH3 doping (g) SiO2 passivation layer deposition and forming Al contacts 4
The fabricated device has a large threshold voltage shift of 2.2 V and the device operated at a low voltage of 6 V. The switching speed between “1” and “0” states of the device for program and erase states was observed to be very fast. The fast switching speeds were due to polarization states of the PZT. The device has a high mobility rate of ~350 cm2-V/second and exhibited a subthreshold swing of 75 mV/decade. The transfer curves for various fatigue cycles are as shown in Figure 16 below.

Figure 16: ID-VG characteristics for various fatigue cycles 4
The ON/OFF ratio of the device was 1.4×108. The reason behind excellent performance of the device was due to the elimination of grain boundaries and creating a buffer layer between the ferroelectric material and Si substrate. The device exhibited shorter retention times due to gate leakage conduction because of trapped electron carriers in the gate oxide interface, and due to self-depolarization of the ferroelectric material. Hence, hafnium-based oxides can be used as the buffer layer to improve these transistors retention time.
Hafnium oxide being a high-k dielectric material has replaced SiO2 as the gate oxide in many devices. The same material when doped with silicon and annealing at the correct temperature is known to exhibit ferroelectric behavior. Rochester Institute of Technology has had students working on making FeFET devices of different ferroelectric materials. Karine Florent, Joseph McGlone, Jackson Anderson, Casey Gonta, Joshua Eschel and Justin Zwick have fabricated devices at the SMFL lab in RIT and analyzed the device behavior. The initial atomic layer deposition of the ferroelectric films was done at NaMLab, Germany. Casey Gonta was the first student to deposit Al:HfO2 in RITs cleanroom and observe the device behavior, but unfortunately his device did not show hysteresis. The reason behind this was due to incorrect annealing of the ferroelectric thin-film. Joshua Eschel however was able to deposit Si:Al:HfO2 which did show hysteresis behavior indicating ferroelectricity in the film. This became the first FeFET device that was deposited and fabricated completely in the SMFL at RIT.
However, the FeFET memory device fabricated by Joseph McGlone for his senior design project is being discussed here. The ferroelectric material used was Si:HfO2 due its ease of integration and high coercive fields. The results of the ferroelectric behavior of fabricated capacitor in RIT was compared to the data provided by NaMLab under same anneal conditions. The obtained P-V hysteresis curves are as shown in Figure 17below.

Figure 17: P-V characteristics of the NaMLab versus RIT capacitor 5
The capacitor from RIT has Metal-Ferroelectric-Insulator-Silicon as its layers and exhibited a remnant polarization of ±9.4 ?C/cm2 which was slightly lesser than NaMLab’s remnant polarization of ±15.2 ?C/cm2 having Metal-Ferroelectric-Metal (MFM) layer. The difference in these values might be because of different film stacks and processing steps used for their fabrication. The polarization states in the ferroelectric layer changed for gate bias voltage sweeps of ±4.5 V. The capacitor exhibited a memory window of 0.6 V which is very less as the polarization state changes quickly. Subthreshold swing of the ON/OFF states was measured to be 110 mV/dec. The threshold voltage of the device after several cycles was observed to reduced due to trapped charges in HfO2 layer. The channel length of the fabricated device was 20 ?m and the ID-VD curves showed punch-through effect due to an increase in the drain bias. This is observed because of high lateral electric field in the channel that results in the gate losing control over the device channel and the device does not turn off in this state. The ID-VD curves is as shown in Figure 18 below.

Figure 18: ID-VD characteristics of Si:HfO2 FeFET 5
CONCLUSION
The demand for larger memory storage devices and high-performance devices has prompted the researching of ferroelectric devices. The property of the ferroelectric device to orient its polarization according to the applied electric field makes it a desirable material for use. This paper discusses the fabrication and performance of different types of ferroelectric field-effect-transistors. On comparing BaTiO3 and SrTiO3 layers, it was observed that BaTiO3 material exhibited anticlockwise ferroelectric behavior, while the SrTiO3 did not. The transfer curves and output characteristics of the device was analyzed. The subthreshold swing of the BaTiO3 device was 190 mV/decade with an ON/OFF ratio of ~104. The device exhibited larger depletion layers and capacitance for this device was analyzed to be a function of circumference of the capacitor and not the area. Hf0.8Zr0.2O2 of 5.5 nm thickness was fabricated for a self-aligned type gate process. Since Hf0.8Zr0.2O2 is a high-k dielectric, the thin layer material was observed to exhibit anticlockwise ferroelectric behavior. The device exhibited breakdown recovery which makes it a desirable property of the device. The defects due to random nucleation in thinner films led to the fabrication of MoS2-PZT FET. The property of PZT to grow over the silicon substrate with minimal lattice mismatch made it desirable due to lower processing costs. The device however had a small retention capacity and the device could not be scaled further. Hence Pb(Zr,Ti)O3 (PZT) devices were fabricated to obtain higher retention capabilities. This device had ultra-fast switching speeds and the highest retention capacity. Growing single devices on rectangular sized grains reduced the defects caused due to lattice mismatch. However, the device had a lot of process steps and exhibited self-depolarization. Hence, hafnium oxide devices were picked as an alternative material.
Silicon doped hafnium-oxide devices were fabricated at RIT and compared to the results obtained from NaMLabs. The RIT fabricated device had lower remnant polarization. This was due to the usage of different gate stacks and type of equipment used. The device can further be studied by depositing other ferroelectric materials to understand the behavior of ferroelectric FETs. The negative capacitance of the ferroelectric material can also be explored for higher retention times and faster switching speeds.
ACKNOWLEGEMENT
The author would like to thank Dr. Robert Pearson for his support and constructive feedback. The author would also like to thank Wallace Library for providing infinite the access to almost every paper available on the internet.

REFERENCES
1 ;Piezoelectric Characterization – Mentor Guide;, Mentors.tanms-erc.org, 2018. Online. Available: http://mentors.tanms-erc.org/mentor-responsibilities/piezoelectric-characterization. Accessed: 04- May- 2018.

2 O. Shoron, S. Raghavan, C. Freeze and S. Stemmer, ;BaTiO3/SrTiO3 heterostructures for ferroelectric field effect transistors;, Applied Physics Letters, vol. 110, no. 23, p. 232902, 2017.

3 K. Chatterjee, S. Kim, G. Karbasian, A. Tan, A. Yadav, A. Khan, C. Hu and S. Salahuddin, ;Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf0.8Zr0.2O2, High Endurance and Breakdown Recovery;, IEEE Electron Device Letters, vol. 38, no. 10, pp. 1379-1382, 2017.

4 Y. Sun, D. Xie, X. Zhang, J. Xu, X. Li, X. Li, R. Dai, X. Li, P. Li, X. Gao and H. Zhu, ;Temperature-dependent transport and hysteretic behaviors induced by interfacial states in MoS2 field-effect transistors with lead-zirconate-titanate ferroelectric gating;, Nanotechnology, vol. 28, no. 4, p. 045204, 2016.

5 J. Park, H. Kim, G. Jang, K. Seok, H. Chae, S. Lee, Z. Kiaee and S. Joo, ;Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor;, Scientific Reports, vol. 6, no. 1, 2016.

6 J. McGlone, ;Ferroelectric HfO2thin films for FeFET Memory Devices;, 34th Annual Microelectronic Engineering Conference, 2016.